![]() Added new information on low voltage ICs.Updated information on practical chips including lower voltage ICs.Ĭhapter 5: IC Specifications and Simple Interfacing.Wrote new subsection on applications of encoders and decoders.Added information on logic probe use in troubleshooting.Ĭhapter 2: Numbers We Use in Digital Electronics.Wrote new section on where digital circuit applications.Added digital application including automotive fuel indicators, vehicle speed sensors and engine control module.A list of chapter-by-chapter changes from the author is included below. The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).Digital Electronics: Principles and Applications has been updated, with new coverage of microcontrollers, memory, interfacing, new self-test questions for students, and more. The open circuit feature allows common busing of the outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. The Q outputs are controlled by a common ENABLE input. Each latch has a separate Q output and individual SET and RESET inputs. Four bits of independent storage with output ENABLEĭata sheet acquired from Harris SemiconductorĬD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches.Holding register in multi-register system.13B, "Standard Specifications for Description of 'B' Series CMOS Devices" Meets all requirements of JEDEC Tentative Standard No.Noise margin (over full package temperature range):.Maximum input current of 1 ♚ at 18 V over full package temperature range 100 nA at 18 V and 25☌.100% tested for quiescent current at 20 V.Standardized symmetrical output characteristics.Separate SET and RESET inputs for each latch.3-state outputs with common output ENABLE. ![]()
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